1. Field of the Invention
This invention relates in general to the testing of microelectronic modules, and more specifically to the use of anti-fuse-controlled enabling or disabling logic circuits, such as the ones used to disable a portion of a memory array found to be defective during wafer-level testing.
2. State of the Art
Semiconductor integrated circuits contain large numbers of electronic components, such as diodes and transistors, built on a single chip. Due to the microscopic scale of these circuits, they are susceptible to component defects due to material impurities and fabrication hazards.
In order to circumvent this problem, redundant components and circuits are built on most chips that can be switched-in in lieu of corresponding circuits found defective during testing. Usually the switching-out of a defective component or circuit, and the switching-in of a corresponding redundant element, is accomplished by using programmable logic circuits which are activated by blowing certain fuses or anti-fuses built into the chip circuitry.
FIG. 1 illustrates an anti-fuse-controlled programmable circuit.
A bank 1 of N programmable logic circuits 2 is interrogated by a Latch.sub.-- Pulse* appearing on a latch pulse line 3 connected to control terminals of the logic circuits 2. Each programmable logic circuit 2 comprises an anti-fuse 4 wired in series with a switching transistor 5 and load transistors 50 and 51 between a supply voltage V.sub.cc and its ground reference V.sub.ss. A node 6 between the anti-fuse 4 and the switching transistor 5 is wired into the input of a driver 7. The output of the driver 7 is typically used to set a latching circuit (not shown) which disables a defective circuit (not shown) and enables a substitute from a redundant circuit bank (not shown). A hysteresis transistor 52 reinforces the output of a low from the driver 7 when the node 6 is high.
Each programmable logic circuit 2 may be programmed by first providing a low Anti-Fuse.sub.-- Isolate* signal to the circuit 2, thereby turning off an isolation transistor 54 and isolating the anti-fuse 4 from the node 6. The programmable logic circuit 2 to be programmed then receives a high Anti-Fuse.sub.-- Select signal, causing an anti-fuse select transistor 56 to turn on in order to couple one terminal of the anti-fuse 4 to ground. A Super Voltage V.sub.SUPER momentarily applied to the other terminal 58 of the anti-fuse 4 then "blows" the anti-fuse 4.
For normal operations, the Anti-Fuse.sub.-- Isolate* signal goes high to turn the isolation transistor 54 on and thereby couple the anti-fuse 4 to the node 6, the Anti-Fuse.sub.-- Select signal goes low to turn off the anti-fuse select transistor 56, and the ground reference voltage V.sub.ss replaces the Super Voltage V.sub.SUPER at the terminal 58 of the anti-fuse 4.
During normal operations, the Latch.sub.-- Pulse* is allowed to pass through the programmable logic circuit 2 only if the ant-fuse 4 has been blown. So long as the anti-fuse 4 isolates the node 6 from the reference ground V.sub.ss, the output of the driver 7 remains low regardless of the presence of the Latch.sub.-- Pulse* on its control terminal, because the hysteresis transistor 52 keeps the input to the driver 7 high, thus maintaining the output of the driver 7 low.
It should be noted that, during normal operations, when the anti-fuse 4 is blown, current is drawn through the load transistor 50, the switching transistor 5, the isolation transistor 54, the load transistor 51, and the blown anti-fuse 4 during the active period of every Latch.sub.-- Pulse*. This type of programmable logic circuit is commonly used in connection with memory chips wherein a Latch.sub.-- Pulse* is usually issued with every memory cycle. As more programmable logic circuits of this type are placed on a wafer and are programmed by blowing their anti-fuses, the cumulative current drawn with every Latch.sub.-- Pulse* can be significant and, obviously, undesirable.
A common solution to this problem is to pulse the programmable logic circuit, i.e., issue a Latch.sub.-- Pulse* only once upon powering up the chip in order to latch-in the proper redundancy scheme or other control option. However, pulsing the circuits during the power up cycle does not guarantee that the proper redundancy or other option then set will not be unlatched sometime later during the operation of the chip as a result of a power surge, background noise or other form of transient. Without any other pulsing of the programmable logic circuit until the next power up, there is no way the circuit can correct itself in such cases of spurious unlatching. Moreover, there is never any guarantee that the correct program can be latched-in with one single initial pulse. It is therefore preferable to issue a Latch.sub.-- Pulse* with every memory cycle, or multiples thereof, to assure not only a correct original latching-in of the programmable scheme, but also an automatic correction of any spurious malfunction.
Accordingly, there is a need in the art for a solution to the excessive drawing of current by banks of such programmable logic circuits used to latch-in redundancy circuits and other programmable options.